1. Field of the Invention
The present invention relates to a switch circuit for switching passing/cutting-off of a signal. Especially, the present invention relates to a technique for forming such kind of a circuit on a semiconductor substrate.
2. Related Art
An analog switch circuit for switching passing/cutting-off of a signal between two types of bi-directional input/output terminals is known. FIG. 8 is a circuit diagram of such kind of a conventional analog switch circuit (U.S. Pat. No. 5,892,387).
The analog switch circuit of FIG. 8 has a PMOS transistor P1 and an NMOS transistor N1 in which source terminals/drain terminals are connected to each other, and a control circuit 1 for controlling on/off of the transistors P1 and N1. One of the source/drain terminals of the PMOS transistor P1 and one of the source/drain terminals of the NMOS transistor N1 are connected to a bi-directional first terminal I/O and another of the source/drain terminals of the PMOS transistor P1 and another of the source/drain terminals of the NMOS transistor N1 are connected to a bi-directional second terminal O/I.
The PMOS transistor P1 and the NMOS transistor N1 are turned on/off in sync with each other. A diode D5 is connected between the source terminal of the PMOS transistor P1 and a substrate, and a diode D6 is connected between the drain terminal and the substrate. A substrate of the NMOS transistor N1 is grounded.
The diodes D5 and D6 are diode parasitized between the source/drain terminal of the PMOS transistor P1 and the substrate. By providing the diodes D5 and D6, in a state that a power supply voltage is not supplied, when the voltages of the first and second voltages become higher than the power supply voltage, the gate voltage of the PMOS transistor P1 is raised from the first and second terminals I/O and O/I through the diodes D5 and D6 and the NAND gate G1 in order to turn off the transistor P1.
The control circuit 1 controls a gate voltage VGP of the PMOS transistor P1 and a gate voltage VGN of the NMOS transistor N1, and has the NAND gate G1 for inverting and outputting a control signal EN and an inverter INV1 for inverting and outputting an output of the NAND gate G1. The PMOS transistor P1 is turned on/off by the output of the NAND gate G1, and the NMOS transistor N1 is turned on/off by the output of the inverter INV1. The diode D1 is connected to the power supply line of the NAND gate G1 and the inverter INV1.
Next, operation of the analog switch circuit of FIG. 8 will be described hereinafter. First of all, when the power supply voltage is supplied, the analog switch is turned on/off in accordance with a logic of the control signal EN. More specifically, if the control signal EN is in high level, the output of the NAND gate G1 becomes low level, the output of the inverter INV1 becomes high level, and the PMOS transistor P1 and the NMOS transistor N1 turn on. Therefore, the signal can be transmitted and received between the first and second terminals I/O and O/I.
If the control signal EN is in low level, the output of the NAND gate G1 becomes high level, the output of the inverter INV1 becomes low level and the PMOS transistor P1 and the NMOS transistor N1 turn off. Therefore, the signal transmission path between the first and second terminals I/O and O/I are cut off.
On the other hand, when the power supply voltage is not supplied, the output of the NAND gate G1 becomes a voltage substantially equal to a cathode voltage of the diode D1, and the output of the inverter INV1 becomes low level. In this state, when a voltage exceeding the power supply voltage is supplied to the first and second terminals, the power supply voltage of the NAND circuit G1 rises via the diodes D5 and D6, and the output voltage of the NAND gate G1 also rises. Accordingly, the PMOS transistor P1 turns off, and the signal transmission path between the first and second terminals I/O and O/I is cut off.
The diodes D5 and D6 are formed in the same well as the PMOS transistor P1, and even if the voltages of the first and second terminals I/O and O/I rise, the voltage of the well does not rise immediately. Therefore, it takes too much time by when the output of the NAND gate G1 changes. Because of this, when the voltages of the first and second terminals rise sharply, the PMOS transistor P1 holds ON state for a certain time. Even if the power supply voltage is not supplied, the first and second terminals are brought into conduction.
For example, when the signal voltage supplied to the first terminal I/O rises sharply, a time lag occurs until when the PMOS transistor P1 turns off. Accordingly, the signal is transmitted to the second terminal, and the second terminal discharges electric charge with time constant of the resistance load and capacitance load. However, when frequency of the signal transmitted and received between the first and second terminals I/O and O/I is high, before discharge is completely finished, operations in which next signal is supplied to the first terminal and again the second terminal is discharged are repeated. Because of this, the second terminal is maintained in a state of high level, and the signal transmission path between the first and second terminals is not cut off.
FIG. 9 is a diagram showing schematic configuration on a semiconductor substrate on which the analog switch circuit of FIG. 8 is formed. As shown in FIG. 9, the PMOS transistor P1 and the diode D5 and D6 are formed in the same well NW.
When the power supply voltage is not supplied to the analog switch circuit, if the voltage of the first or second terminal I/O or O/I rises sharply, the N well NW is charged by the voltage.
The sizes of the PMOS transistor P1 and the NMOS transistor N1 are large as many as several dozen times compared with the other transistors constituting the control circuit 1. As an example, transistor width of the PMOS transistor P1 of the inverter INV1 in the control circuit 1 is 10 μm, and the transistor width of the PMOS transistor P1 is 500 μm.
Because of this, the size of the N well NW shown in FIG. 9 becomes large, and the capacitance (about 5 pF) of the capacitor C for the semiconductor substrate also becomes large. Accordingly, delay of about 5 ns occurs due to resistance component (about 1 kΩ) of the N well NW and a time constant.